The present invention relates to a multi-chip module in which a plurality of semiconductor chips are mounted on a mounting board.
In recent years, mobile phones, note type computers, PDA (Personal Digital Assistance) or the like are rapidly coming into wide use, while miniaturization and weight reduction and higher performance of these consumer-oriented electronic systems are rapidly being pursued. In order to realize these, there is a need for a technology for densely packing semiconductor devices, such as a CPU, microprocessor, logic, and memory, and passive electronic components and assembling them into a system module.
Although an ultimate aspect of the system module is a system-on-chip in which all devices are made into a single chip, it is difficult to make different devices into a chip at the same time, and thus there is fear for a reduction in yield. Further, such a system module is made on orders for each of products and tends to be manufactured in small volumes with different configurations. Therefore, there is a problem that newly designing of such products from the stage of devices may be not cost-justified. Thus, the technology development of MCM (Multi-Chip Module) is actively pursued, in which a plurality of separately manufactured chips are densely mounted with wiring length as short as possible to assemble into one system module.
An example of conventional MCM""s is described in JP-A-10-126044 specification, which discloses an MCM structure, wherein a plurality of semiconductor chips are flip-chip mounted on a base board via solder and a sealing resin is flowed between the semiconductor elements and the base board.
Further, JP-A-2000-196008 specification discloses a multi-chip type semiconductor device, in which semiconductor chips of not less than three are arranged on a board in a planar manner, electrical connections between the chips are made with fine lines, and the whole of the semiconductor chips and fine lines are covered with a sealing resin, and then a ball grid array which becomes as external electrodes is formed on a back surface of the board.
However, any of JP-A-10-126044 and JP-A-2000-196008 specification does not disclose how to improve the reliability of the whole multi-chip modules to thermal stress or the like.
Therefore, the invention has an object to provide a multi-chip module having high reliability to thermal stress or the like.
In order to overcome the above problems, the multi-chip module according to the invention will be structured as follows.
A first invention is for a multi-chip module in which a plurality of semiconductor chips having semiconductor elements are mounted on a mounting board. At least two of the semiconductor chips have chip electrodes, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and stress-relaxation layers intervening between the lands and the semiconductor chips. The semiconductor chips are mounted on the mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.
When improving the reliability of the multi-chip module of the present invention, in order that the reliability of a plurality of stress-relaxation layered semiconductor chips mounted therein can be matched with the improved reliability of the multi-chip module, the chip having a larger outermost terminal distance should have a stress-relaxation layer able to absorb larger strain. As the material of the stress-relaxation layer is smaller in elasticity and thicker in thickness, the stress-relaxation layer has a higher ability to absorb strain. When the materials of the stress-relaxation layers are of the same degree, the stress-relaxation layer of the chip having a larger outermost terminal distance is made thick, such that a difference in the reliability of their external terminals can be made smaller.
A plurality of stress-relaxation layered semiconductor chips mounted on a mounting board are a small package of the chip size in which the external terminals are placed within a plane of the semiconductor chip or in a range close thereto. When temperature changes are applied to the state where the semiconductor chips are mounted on a board, strains are caused by a difference in thermal expansion between the semiconductor chips and the mounting board. Although these strains tend to concentrate on the external terminals sandwiched therebetween, it is possible to absorb the strains by deformation of the stress-relaxation layers intervening between the external terminals and the semiconductor chips to improve the life of the external terminals in temperature cycles. The reliability of the external terminals can be improved without the reinforcement of under-fills, which has been used in multi-chip modules based on conventional bare chip mountings. Therefore, the under-fill process can be omitted in mounting, thus resulting in low cost. Further, the chips are repairable after mounting. In this case, it is desirable from the viewpoints of effective cooling that there are spaces around the external terminals. Also, because the interconnections are on a chip and the external terminals are arranged at a pitch larger than the pitch of chip electrodes, the chips is easy to be mounted on a board and also high-density mounting boards are not needed. Further, because the stress-relaxation layer can absorb a displacement difference caused by the thermal expansion, the stress generated in the chips can be reduced. Further, the cracks in chips can be suppressed. These can provide multi-chip modules of high reliability at low cost. Also, the multi-chip modules are easy to be mounted on a board and able to suppress cracks in chips.
Further, it is preferable to form a multi-chip module, in which at least two of the semiconductor chips have chip electrodes of the semiconductor chips, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and stress-relaxation layers intervening between the lands and the semiconductor chips, and are placed on the mounting board via the external terminals, and spaces are provided around the external terminals, and a distance between an end of a first semiconductor chip having the stress-relaxation layer and an end of a second semiconductor chip having the stress-relaxation layer placed adjacent to the first semiconductor chip is less than 1 mm.
In the under-fill mounting, the under-fill is formed so as to spread from ends of the semiconductor chip outward to the surface of the mounting board (under-fill fillet). Also, in order to insert a nozzle for injecting under-fill, a space of 1 to 2 mm is required between adjacently mounted semiconductor chips. On the other hand, when the under-fills are omitted in semiconductor chips having stress-relaxation layers in the multi-chip module of the invention, the multi-chip module can be formed in the same size as the semiconductor chips, and thus a plurality of semiconductor chips can be mounted more densely. In this case, effective cooling is possible in spite of high-density mounting. For example, the space between the adjacent semiconductor chips may be less than 1 mm or 0.5 mm or less than 0.5 mm to increase the mounting density. Further, the space can be narrowed to the extent such that the ends of both chips will not come into contact with each other.
Also, a second invention provides a multi-chip module comprising a plurality of semiconductor chips having the stress-relaxation layers, characterized in that the stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a projected area of the external terminal positioned at the outermost end larger than that projected area of the first semiconductor chip.
The life of an external terminal changes depending on the size of the external terminal. The larger the size of an external terminal is, the larger the strain absorbed by the external terminal itself is, thus improving the reliability of the external terminal. Therefore, when the pitch of external terminals arranged is small and the size of the external terminals is also small, as described above, the thickness of the stress-relaxation layers is made so thick as to reduce a disparity in the stress-absorbing ability as a whole, thereby allowing an improvement in the whole reliability.
However, when merit of a reduction in cost due to unification of processes is larger, the thickness of the stress-relaxation layer necessary for ensuring the reliability of a stress-relaxation layered semiconductor device of the largest outermost-terminal-distance may be also formed as the thickness of the stress-relaxation layer of the other stress-relaxation layered semiconductor devices.
Further, for the above described multi-chip module, it is preferable that in at least one of stress-relaxation layered semiconductor devices, the interconnections, the lands, the external terminals, and the end of the stress-relaxation layer are formed inside the end of the semiconductor chip. In this case, it is preferable that the interconnections are formed with thin film interconnections, for example.
Although Si has been conventionally mainstream as a material of semiconductor chips, in recent years, compound semiconductors such as GaAs and InP has been being used for high speed signal processing and optical signal processing in communication system. These compound semiconductors are generally more brittle than Si, and thus the above problem of cracks in chips may be noticeable. In the multi-chip module according to the invention, the stress-relaxation layered semiconductor device is applied to semiconductor chips made of the compound semiconductors as described above, thereby allowing a reduction in the stresses applied to the semiconductor chips and the prevention of cracks in chips.